1. Technical Field
The present disclosure relates to the field of power modeling and power estimation of Integrated Circuit (IC) blocks during the design stage for subsequent testing of the IC blocks. More particularly, the present disclosure relates to optimization of test time and test power during scan testing of a system on chip ICs, while providing maximum test coverage.
2. Description of the Related Art
The power grids for today's system-on-chip (SOC) IC testers are designed for maximum power consumption. Typical SOCs are tested by the testers based on the expected worst case power for normal operation mode of the SOCs, which allows for switching a very low percentage of the circuit elements during normal operation. In related art scan testing, the entire chip is tested at the same time, so a much larger percentage of circuit elements switch, causing the power to be too high for the tester's power grid. The alternative in the related art is to divide the long scan chain (which includes all the circuit elements of the SOC) into a small number of scan groups. Then, during scan testing each test covers one scan group, while the remainder of the chip is inactive. This way the total power consumption is within acceptable limits of the tester. However, as the number of scan groups increases, the total test time and test cost increases.
Typically scans are run at the expected maximum normal operational speed, also referred to as ‘at speed’, for each of the scan blocks of a SOC, with the aim of providing a high speed test with maximum test coverage. This results in an increase in the number of active operational elements switching simultaneously, when compared to a functional test of the blocks using a test program, and hence the power consumption may exceed the allowed tester power supply capability. This results in an inability to provide test coverage of the device, using scan chains, without exceeding the power bus capacity of the tester as no prior knowledge of the power dissipation is available till an actual scan test is run.
In some cases it may be possible to solve the problem by slowing down the scan frequency, which increases test time and test cost. It also eliminates the test of the circuits at speed creating uncertainty of a circuit's capability to function at speed under all conditions.
Another possibility is to design the SOC so that it is divided into multiple small scan groups where each scan group is small enough to ensure that the power dissipation is small when separately tested. Since individual scan group testing takes a definite time to program and test, for providing the necessary test coverage, the SOC testing time is increased in proportion to the number of scan groups of the IC. Combining scan groups to enable optimum number of test groups is difficult as it has to be done before the chip is fabricated and before the actual power consumption is known. Even after combining the scan groups this way, the combinations have to be verified to ensure that interactions between circuit components and peripherals do not cause the combination to miss out on desired test coverage and also exceed the power limit of the tester.
Even though the need is acute, today there is no good way to ensure that some particular division of the SOC into scan groups, either functional or otherwise, is optimum before the SOC is ready for test. An optimum set of scan groups is where each group is “safe”, i.e., within the power range allowable for the tester's power grid, yet optimized for the minimum number of scan groups to save test time. There is no method in the related art for achieving the optimization of scan partitions at the design stage of the SOC.